An output section of a three-level inverter is known, for instance, from the publication "A New Neutral-Point-Clamped PWM Inverter" in "IEEE Transactions on Industry Applications", Vol. IA-17, No. 5, September/October 1981, Pages 518 to 521, as is shown in FIG. 1 of that publication.
German Offenlegungschrift No. 32 44 623 shows in its FIGS. 5 and 6, wiring arrangements for two antiparallel circuits forming the power section in one phase of a bridge inverter. Each antiparallel circuit has one semiconductor switching element and a corresponding bypass diode. The bypass diodes serve as the switching-off relief of the semiconductor switching elements. The rate of rise of the recurring positive forward voltage is limited during the interruption process and thereby, the occurrence of excessively high power losses in the respective semiconductor switching elements is avoided. In one embodiment of this known wiring arrangement, a series circuit comprising a first switching-off relief diode and a switching-off relief capacitor is connected to one of the two antiparallel circuits in one phase of the bridge inverter. The junction point of these two wiring elements is in electrical contact with the junction point between the elements of a second series circuit via a second switching-off relief diode. The second series circuit comprises a d-c load and a storage capacitor and is connected parallel to the supplying d-c voltage source.
An additional switching-on relief choke limits the rate of rise of the load current upon switching on of one of the semiconductor switching elements. The relief choke is connected in series with the junction point provided for connection to the potential of the d-c voltage source of the antiparallel circuit that is provided with the wiring arrangement described above. Depending on the circuit design, this switching-on relief choke can also be formed by the unavoidable parasitic stray inductances of the leads. The switching-on relief choke serves at the same time as a so-called reversing choke. This is done in order to bring the switching-off relief capacitor of one of the semiconductor switching elements of the inverter to such a charging state that it can have a relief effect during a subsequent disconnection of one of the semiconductor switching elements.
In such a switching-off process, the load current driven by the switching-on relief choke is diverted via the first switching-off relief diode to the switching-off relief capacitor. In this manner, the current through a semiconductor switching element to be switched off is interrupted nearly as a step function. Also, the rate of rise of the recurring positive blocking voltage in the forward direction is limited due to the finite charge reversal rate of the switching-off relief capacitor.
After the switching-off relief capacitor has been charged to the value of the d-c voltage supply, the current of the switching-on relief choke leads until its complete decay, to a further charging of the then effective parallel circuit comprising the switching-off relief capacitor and the storage capacitor. While the two capacitors are only slightly overcharged so that the overvoltage stress of the semiconductor switching element to be switched off remains small, this property of the wiring can further be aided by the provision that the storage capacitor has a considerably larger capacity than the switching-off relief capacitor. The storage capacitor therefore has the purpose of temporarily storing the energy of the switching-off relief choke serving to relieve the switching on process and for switching off. So that the storage capacitor can carry this out for every switching cycle in the same manner, it is periodically discharged via the d-c load connected in series. An ohmic resistor can be used as the d-c load. In another known embodiment the power loss produced during the switching relief of the semiconductor switching element of the respective inverter phase is not canceled, but instead returned to the supplying d-c voltage source by a feedback circuit.
During the switching-off of one semiconductor switching element of one phase, the series circuit of the first switching-off relief diode and the switching-off relief capacitor forms a relief path. During the switching-off of the other semiconductor switching element of the phase, the series circuit of the switching-off relief capacitor, the second switching-off relief diode and the storage capacitor forms a longer relief path for the load current to be commutated off, and therefore this circuit has a slight asymmetry. This manifests itself in a slightly larger parasitic stray inductance in the relief path for the other semiconductor switching element and thus in a slightly higher voltage stress during the switching-off of this semiconductor switching element.
In European Pat. Application No. 88110741.1, a device for the low-loss wiring of the semiconductor switching element of a three-level inverter is described. The circuitry described there, however, has the disadvantage that a multiplicity of components is necessary for achieving the desired switching relief effect. It is advantageous for the functioning of the known circuitry to provide modifications in the basic circuit of the three-level inverter by using additional switching-on relief chokes in the output sections. This increases the cost of the circuit further.
A problem posed by the prior art is to provide an arrangement for relieving as uniformly as possible the switching-on and off of semiconductor switching elements in the phase of a three-level inverter, which uses as few components as possible.
The present invention provides that the circuitry known from German Offenlegungsschrift No. 32 44 623 for the semiconductor switching elements in the phases of an inverter in a bridge circuit can also be used for the semiconductor switching elements in the phases of a three-level inverter. For applying this known circuitry arrangement to a three-level inverter, no adaptations in the output section of the three-level inverter are necessary. It has furthermore been found to be particularly advantageous that the known wiring arrangement in a first embodiment of the invention can be used without change to the internal circuit. It is a further advantage of the invention that, if necessary, other wiring arrangements which likewise have a relief effect for the switching, especially RCD wiring arrangements, can be connected without detrimentally affecting the functioning of the circuitry according to the invention.
The problems discussed above are solved in the present invention by providing a three-level inverter having at least one inverter phase with a series arrangement of first, second, third and fourth antiparallel circuits, each antiparallel circuit including a semiconductor switching element and a bypass diode. A phase output is formed by a junction point of the second and third antiparallel circuits, while a d-c voltage source supplies voltage to the phase. First and second switching-on relief chokes couple this series arrangement to the positive and negative potentials of the d-c voltage source. First and second voltage divider capacitors are coupled to be supplied by the d-c voltage source, with the junction point formed between the first and second voltage divider capacitors. A first decoupling diode is coupled between the junction point between the first and second voltage divider capacitors in a junction point between the first and second antiparallel circuits. A second decoupling diode is coupled between the junction point between the first and second voltage divider capacitors and a junction point between the third and fourth antiparallel circuits.
The invention provides a means for relieving the semiconductor's switching elements during a switching-off process. This means for relieving includes a first series circuit having a first wiring diode and a first switching-off relief capacitor, this first series circuit shunting the first antiparallel circuit. The second series circuit having a second wiring diode and a second switching-off relief capacitors shunts said fourth antiparallel circuit. The means for relieving includes a third series circuit having a first storage capacitor and a first d-c load, this third series circuit being shunted across the first voltage divider capacitor. A fourth series circuit has a second storage capacitor and a second d-c load, and is shunted across the second voltage divider capacitor. A third wiring diode is coupled between the junction point of the first wiring diode and the first switching-off relief capacitor and the junction point of the first storage capacitor and the first d-c load. A fourth wiring diode is coupled between the junction point of the second wiring diode and the second switching-off relief capacitor and the junction point of the second storage capacitor and the second d-c load.